1. Field of the Invention
The present invention relates to a flip chip structure, the method to manufacture the same and, more particularly, to a flip chip substrate structure that applies to without plated through hole sand improves circuit integration, and a method to manufacture flip chip substrates with a streamlined process.
2. Description of Related Art
With the development of the IT industry, the research in the industry is gradually turning to multifunctional and high performance electronic products. To meet the demands for high integration and miniaturization of semiconductor packaging, the circuit boards providing circuit connections among active and passive components are evolving from double layer circuit boards to multi-layer circuit boards in order to expand available layout areas on circuit boards within limited spaces by interlayer connection techniques, so as to accommodate high circuit layout density.
The semiconductor packaging structures known in the art are fabricated by adhering a semiconductor chip on the top of the substrate, proceeding with wire bonding or flip chip packaging, and then mounting solder balls on the back of the substrate for electrical connection. Though a high pin quantity can be obtained, operations at higher frequencies or speeds are restricted due to unduly long lead routes and consequent limited performance. Besides, multiple connection interfaces are required in conventional packaging, leading to increased process complexity.
In the method to manufacture flip chip substrates, the fabrication of a substrate begins with a core substrate, which is then subjected to drilling, electroplating, hole-plugging, and circuit formation to accomplish the internal structure. A multi-layer substrate is then obtained through circuit build up processes, as the method to fabricate circuit build up multi-layer circuit boards shown in FIG. 1A to FIG. 1E. Referring to FIG. 1A, a core substrate 11 is first prepared, which is composed of a core layer 111 having a predetermined thickness and circuit layers 112 formed on the surface thereof. Meanwhile, a plurality of plated through hole 113 are formed in the core layer 111 to electrically connect the circuit layers 112. Referring to FIG. 1B, the core substrate 11 is subjected to a circuit build up process so as to overlay a dielectric layer 12 on the surface of the core layer 11, wherein the dielectric layer 12 has a plurality of vias 13 that the circuit layer 112 are exposed to the vias 13. Referring to FIG. 1C, a seed layer 14 is formed by electroless plating or sputtering on the dielectric layer 12, wherein a patterned resist layer 15 is formed on the seed layer 14, and plural openings 150 are formed in the resist layer 15 to expose the portions of seed layer that are set to be a patterned circuit layer. Referring to FIG. 1D, a patterned circuit layer 16 and plural conductive vias 13a are formed in the openings of the resist layer by electroplating, the resist layer 15 and the portions of seed layer 14 covered therebeneath are removed, such that a first circuit build up structure 10a is formed. Referring to FIG. 1E, a second circuit build up structure is formed on the outer surface of the first circuit build up structure in the same manner, repeating the same circuit build up procedures to form a multi-layered substrate.
However, the aforementioned process begins with a core substrate, which is subjected to drilling, electroplating, hole-plugging, and circuit formation to form the internal structure. Then a multi-layer substrate is formed through a circuit build up process. The method has problems such as low integration, multiple layers, long leads and high resistance, rendering it less applicable to high-frequency semiconductor packaging substrates. Due to its multiple layers, the process procedures are complex and the process cost is higher.